DE: Unit 3 Review

Front

What is the limitation of the 74LS93 counter?

Back

It can only be used to implement up counts.

Front

What is the primary difference between a D flip-flop and a D latch?

Back

The clock input is edge sensitive for the flip-flop and level sensitive for the latch.

Front

What is the purpose of asynchronous inputs (Preset & Clear) in a flip-flop?

Back

To override the clock/data inputs and force the outputs to a predefined state

Front

What is the function of the Enable (EN) input in a transparent D-latch?

Back

To control when the latch is transparent or latched

Front

Which type of flip-flop has a positive edge-triggered clock input?

Back

D flip-flop

Front

What is the timing interval before the active transition of the clock signal during which the data input must be maintained called?

Back

Setup Time (tS)

Front

Which component is used to force the output of a flip-flop to a predefined state? Options: Data input, Clock input, Enable input, Asynchronous inputs (Preset & Clear)

Back

Asynchronous inputs (Preset & Clear)

Front

What is the function of the J and K inputs in a J/K flip-flop?

Back

To determine the next state of the flip-flop based on the current state and the clock input

Front

Which flip-flop has excitation table with J and K inputs?

Back

J/K flip-flop

Front

What is the main function of the 74LS163 Synchronous 4-Bit Binary Up Counter?

Back

Counting up