Unit 3 Assessment

Front

What happens to the output Q when J=0, K=0, and CLK is at the rising edge?

Back

No Change

Front

The flip-flop's CLOCK input is ______ sensitive, meaning the flip-flop's output changes on the ______ (rising or falling) of the CLOCK input.

Back

edge

Front

The configuration is nonstable when either the preset and/or clear inputs return to their inactive (____) level.

Back

HIGH

Front

A shift register is a group of flip-flops arranged so that the values stored in the flip-flops are shifted from one flip-flop to the next for every ____.

Back

clock pulse, clock

Front

What does SSI stand for in the context of Digital Logic?

Back

Small Scale Integration

Front

Which of the following best describes an asynchronous counter? A counter that operates in sync with a clock signal, A counter that operates independently of a clock signal, A counter that uses synchronous flip-flops, A counter that uses asynchronous flip-flops.

Back

A counter that operates independently of a clock signal

Front

Calculate the number of states for a system with 3 flip-flops.

Back

8 states.

Front

What type of counter is the 74LS93 IC?

Back

4-bit ripple counter

Front

What type of counter is shown in the design example circuit diagram?

Back

4-Bit Asynchronous, Modulus-13 Counter

Front

What is a trade-off for the convenience of an all-in-one package in most MSI integrated circuits?

Back

Lack of design flexibility