AI.1.1.System Architecture

AI. 1.1. System Architecture

By Mr. Shingari

Multiple Choice

Which register receives an instruction from the address in the memory address register?

• Accumulator
• Memory data register
• Interrupt register
• Program counter

Multiple Choice

The main components of a computer, including main memory and the processor are connected together by a series of what?

• Connectors
• Buses
• Pathways
• Interconnectors

Multiple Choice

One purpose of the control unit is to?

• To perform calculations in the CPU
• To control peripherals using device drivers
• Control the loading of data from the hard disk to RAM
• Send signals to control how data moves around the CPU

Multiple Choice

Which of the following types of memory is in the processor?

• Main memory (ROM)
• Main memory (RAM)
• Registers
• Virtual memory

Multiple Choice

What is the purpose of the accumulator?

• To fetch the next instruction to calculate data
• To execute a calculation
• To store the results of calculations
• To decode an instruction to calculate a total

Multiple Choice

Which bus carries the location of where data should be read/written to and from?

• Data
• Control
• Serial
• Address

Multiple Choice

The value in the program counter is passed to which register during a fetch operation?

• Memory data register
• Memory address register
• Accumulator
• Program counter

Multiple Choice

Which of these is a function of the ALU?

• Cache
• Fetch
• Arithmetic
• Control

Multiple Choice

Which of these is a function of the ALU?

• Logic
• Fetch
• Cache
• Control

Multiple Choice

Which of these is a function of the ALU?

• Bus check
• Speeds up the processor
• Binary shift
• Stores frequently used instructions

Multiple Choice

Which register always holds the results of calculations from the ALU?

• Accumulator
• Memory data register
• Memory address register
• Program counter

Multiple Choice

The accumulator and memory address register are used by which component in the CPU to perform calculations?

• Interrupt handler
• Arithmetic Logic Unit
• Control unit
• Decode unit

Multiple Choice

Which bus carries signals to co-ordinate all of a computer activities?

• Address
• Serial
• Data
• Control

Multiple Choice

What does the current instruction register hold?

• Address of the next instruction to be executed
• Data being transferred to and from main memory
• Address of the instruction or piece of data to be fetched or stored
• The current instruction to be executed

Multiple Choice

Which register always holds the address of the next instruction?

• Memory address register
• Accumulator
• Memory data register
• Program counter

Multiple Choice

What does the memory address register hold?

• Address of the instruction or piece of data to be fetched or stored
• Data being transferred to and from main memory
• Address of the next instruction to be executed
• The current instruction to be executed

Multiple Choice

Which of these program instructions can cause the program counter to change the value it stores?

• A store instruction e.g. to put the value of the accumulator back into RAM
• A jump instruction e.g. condition or iteration
• A load instruction e.g. to load a value into the accumulator
• An add instruction e.g. to sum two numbers

Multiple Choice

The current instruction register holds the assembly language code 'BRP 6'. If the accumulator holds the value 2, to which register is the number 6 sent to?

• Accumulator
• Program counter
• Memory data register
• Memory address register

Multiple Choice

The current instruction register holds the assembly language code 'BRZ 6'. If the accumulator holds the value 0, to which register is the number 6 sent to?

• Memory data register
• Memory address register
• Program counter
• Accumulator

Multiple Choice

The current instruction register holds the assembly language code 'LDA 6'. To which register is the number 6 sent to?

• Program counter
• Memory data register
• Memory address register
• Accumulator

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Multiple Choice

Which of the following is an advantage of pipelining?

• A. Instruction throughput increases.

• B. Faster ALU can be designed when pipelining is used.

• C. Pipelining increases the overall performance of the CPU.

• D. All of the above

Multiple Choice

CISC code can better utilise pipe-lining as the time needed for each operation can be predicted.

• TRUE

• FALSE

Multiple Select

Pipelining means...

• Running the fetch-decode-execute cycle more efficiently

• Waiting for a full fetch-decode-execute cycle to complete before starting the next

• Fetches the next instruction while the previous instruction is still decoding

• CISC processors can run more efficiently

• RISC processors can run more efficiently

Multiple Choice

Cannot support pipelining

• CISC

• RISC

Multiple Choice

______ is the process where different parts of the CPU are used for performing tasks

• Caching

• Pipelining

• Core

• Clock speed

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Multiple Choice

Which of these describes a classic von Neumann architecture?

• Control unit is more complicated to handle separate instruction and data buses
• The processor needs more than one cycle to fetch, decode and execute an instruction
• Data transfers and instruction fetches from memory can be done at the same time
• Uses separate memory addresses for instructions and data

Multiple Choice

Which of these describes a classic von Neumann architecture?

• Has one data bus for the transfer of instructions and data between the CPU and RAM
• Has an address bus and a data bus that can be used to transfer instructions and data between the CPU and RAM
• Has two data buses for the transfer of instructions and data between the CPU and RAM
• Has an instruction bus and a data bus for the transfer of instructions and data between the CPU and RAM

Multiple Choice

Which of these describes a classic von Neumann architecture?

• Data transfers and instruction fetches can be performed at the same time
• Uses separate memory address space for instructions and data
• The processor only requires one cycle to complete an instruction
• Data transfers and instruction fetches from RAM cannot be performed at the same time

Multiple Choice

Which computer architecture holds both programs and data in same main memory?

• Harvard
• Modern
• Contemporary
• Von Neumann

Multiple Choice

Which of these statements describes a classic von Neumann architecture?

• Reading and writing data can be done at the same time as fetching instructions
• Each memory unit has its own bus
• One systems bus connects the processor to the memory
• Instructions and data stored in separate memory units

Multiple Choice

Which of these statements describes a classic von Neumann architecture?

• Each memory unit has its own bus
• Reading and writing data can be done at the same time as fetching instructions
• Instructions and data stored in separate memory units
• Shared memory space for instructions and data

Multiple Choice

Which of these statements describes a classic von Neumann architecture?

• Instructions and data stored in separate memory units
• Each memory unit has its own bus
• Reading and writing data can be done at the same time as fetching instructions
• A single control unit follows fetch, decode, execute cycle one instruction at a time

Multiple Choice

Which of these statements describes a Harvard architecture?

• Instructions and data stored in separate memory units
• One system bus connects processor to the memory
• A single control unit follows fetch, decode, execute cycle one instruction at a time
• Shared memory space for instructions and data

Multiple Choice

Which of these statements describes a Harvard architecture?

• One system bus connects processor to the memory
• A single control unit follows fetch, decode, execute cycle one instruction at a time
• Fetching instructions and writing data can be done at the same time
• Shared memory space for instructions and data

Multiple Choice

Which of these statements describes a Harvard architecture?

• Each memory unit has its own bus
• One system bus connects processor to the memory
• A single control unit follows fetch, decode, execute cycle one instruction at a time
• Shared memory space for instructions and data

Exam questions 1.1. System architecture​

Answer the exam questions on teams for topic 1.1.

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