H CS - Computer structure

Reorder

Reorder the steps of the memory write operation.

• The MAR sets up the address bus with the memory location to be read from.

• The MDR passes the data to be written to the data bus.

• The write line on the control bus is activated by the processor.

• The data bus transfers the data to the memory address specified on the address bus.

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Open Ended

Explain why a processor with larger cache would outperform an identical processor with smaller cache. (2 marks) 

​Answer

• ​larger cache stores more instructions/data

• more cache hits/fewer cache misses

• reduces fetches from main memory

  1 mark for each bullet

  Maximum 2 marks

Match

Match the system factor with the correct positive effect on system performance.

• Increased data bus width

• Increased cache memory

• Increased clock speed

• Increased processor cores

> bits transferred in a single operation

reduce number of accesses to main memory

More fetch-executes per clock pulse

Simultaneous execution of instructions

• > bits transferred in a single operation

• reduce number of accesses to main memory

• More fetch-executes per clock pulse

• Simultaneous execution of instructions