Search Header Logo
H CS - Computer structure

H CS - Computer structure

Assessment

Presentation

Computers

8th Grade

Easy

Created by

G Alexander-Doyle

Used 7+ times

FREE Resource

15 Slides • 6 Questions

1

media

2

media

3

media

4

media

5

media

6

Reorder

Reorder the steps of the memory write operation.

The MAR sets up the address bus with the memory location to be read from.

The MDR passes the data to be written to the data bus.

The write line on the control bus is activated by the processor.

The data bus transfers the data to the memory address specified on the address bus.

1
2
3
4

7

media

8

Fill in the Blanks

Type answer...

9

Fill in the Blanks

Type answer...

10

Fill in the Blanks

Type answer...

11

media

12

media

13

14

media

15

Open Ended

Explain why a processor with larger cache would outperform an identical processor with smaller cache. (2 marks) 

16

​Answer

  • larger cache stores more instructions/data

  • more cache hits/fewer cache misses

  • reduces fetches from main memory

    1 mark for each bullet

    Maximum 2 marks

17

media

18

media

19

Match

Match the system factor with the correct positive effect on system performance.

Increased data bus width

Increased cache memory

Increased clock speed

Increased processor cores

> bits transferred in a single operation

reduce number of accesses to main memory

More fetch-executes per clock pulse

Simultaneous execution of instructions

20

media

21

media
media

Show answer

Auto Play

Slide 1 / 21

SLIDE