H CS - Computer structure

Reorder

Reorder the steps of the memory write operation.

• The MAR sets up the address bus with the memory location to be read from.

• The MDR passes the data to be written to the data bus.

• The write line on the control bus is activated by the processor.

• The data bus transfers the data to the memory address specified on the address bus.

1

2

3

4

• 1
• 2
• 3
• 4

Fill in the Blank

What is missing from step 2 of the fetch-execute cycle?

1.The MAR sets up the address bus with the memory location to be read from.

2.The ____ ____ on the control unit is activated by the processor.

3.The data from the memory address is placed on the data bus and transferred back to the instruction register.

4.The instruction in the instruction register is then interpreted by the decoder and carried out.

Fill in the Blank

Which component is missing from step 1 of the fetch-execute cycle?

1.The ___ sets up the address bus with the memory location to be read from.

2.The read line on the control unit is activated by the processor.

3.The data from the memory address is placed on the data bus and transferred back to the instruction register.

4.The instruction in the instruction register is then interpreted by the decoder and carried out.

Fill in the Blank

Which component is missing from step 3 of the fetch-execute cycle?

1.The MAR sets up the address bus with the memory location to be read from.

2.The read line on the control unit is activated by the processor.

3.The data from the memory address is placed on the ____ ___ and transferred back to the instruction register.

4.The instruction in the instruction register is then interpreted by the decoder and carried out.

Open Ended

Explain why a processor with larger cache would outperform an identical processor with smaller cache. (2 marks) 

​Answer

• ​larger cache stores more instructions/data

• more cache hits/fewer cache misses

• reduces fetches from main memory

  1 mark for each bullet

  Maximum 2 marks

Match

Match the system factor with the correct positive effect on system performance.

• Increased data bus width

• Increased cache memory

• Increased clock speed

• Increased processor cores

> bits transferred in a single operation

reduce number of accesses to main memory

More fetch-executes per clock pulse

Simultaneous execution of instructions

• > bits transferred in a single operation

• reduce number of accesses to main memory

• More fetch-executes per clock pulse

• Simultaneous execution of instructions