DE SSD & Flip Flops

The asynchronous input on this flip-flop is

• J
• K
• clear
• Q
  Clock

This  flip-flop transitions on

• the falling clock edge.
• the rising clock edge.
• high clock level.
• low clock level.

What signal activates this Preset input?

• 0
• 1
• Low clock level
• High clock level

This flip-flop transitions on

• the rising clock edge
• the falling clock edge
• high clock level.
• low clock level.

If Pre=1, Clr=1, J=0, and K=1, what will Q be on the next transition edge?

• 0
• 1
• Impossible to tell
• the opposite of present Q

What synchronous inputs would output Q' on the next transition edge?

• J=0, K=0
• J=0, K=1
• J=1, K=0
• J=1, K=1

What synchronous inputs would output Q=0 on the next transition edge?

• J=0, K=0
• J=0, K=1
• J=1, K=0
• J=1, K=1

Which rule gives Q on the transition edge?

• Q = D'
  

• Q = D
• Q = Clock
• Q = Clock'

Preset forces Q to

• 1
• 0
• Q'
• No change

What logic values need to be placed on the inputs (a) through (g) of the common cathode seven segment in order to display the number 2?

• A

• B

• C

• D