2.2 Machine Instruction Cycle

The phases in the Central Processing Unit (CPU) process cycle.

• Fetch - Decode - Execute Cycle

• Sequential processing

• Parallel computing

• Multitasking

It isresponsible for the timing and execution of the various

register transfers required to fulfill an instruction held in the CIR.

• Arithmetic unit

• Logic unit

• Control unit

• Registers

What is the name of the unit that manages the four basic operations (fetch, decode, execute, and store) of the Fetch Execute Cycle?

• Control unit

• Registers

• Arithmetic unit

• Logic unit

What are the three phases of the machine instruction cycle? (choose all applicable)

• Fetch

• Decode

• Execute

• Copy

• Handshake

A = 5

B = 6

What is the name of the unit in the CPU that would perform operation A > B?

• ALU

• CU

• MAR

• MDR

Which of the following unit in Von Neumann Model store instructions during the Fetch - Execute Cycle?

• Control unit

• Registers

• Arithmetic unit

• Logic unit

It is the part of the instruction fetched from the main memory that specifies the operation to be performed.

• Data

• Input

• Opcode

• Operand

It is the part of the instruction fetched from the main memory that specifies the data that needs to be acted on.

• Data

• Input

• Opcode

• Operand

This register holds the address of the next instruction to be executed.

• MAR

• MDR

• PC

• CIR

• ACC

This register receives the memory address from the program counter and passes the address to the main memory using Address Bus.

• MAR

• MDR

• PC

• CIR

• ACC