Digital Logic Design

Digital Logic Design

University - Professional Development

20 Qs

quiz-placeholder

Similar activities

Spreadsheet Fundamentals - Quiz2

Spreadsheet Fundamentals - Quiz2

University

20 Qs

Algoritma Remedial RPL

Algoritma Remedial RPL

University

20 Qs

Chapter 8 - Memory Management Strategies

Chapter 8 - Memory Management Strategies

University

15 Qs

HTML - Introdução

HTML - Introdução

University

16 Qs

Hexadecimal - decimal y binario

Hexadecimal - decimal y binario

University

17 Qs

Skill Competition Quiz 2024

Skill Competition Quiz 2024

10th Grade - University

20 Qs

Introducción Redes Tele1 IB

Introducción Redes Tele1 IB

10th Grade - University

15 Qs

Python Quiz

Python Quiz

University

15 Qs

Digital Logic Design

Digital Logic Design

Assessment

Quiz

Computers

University - Professional Development

Practice Problem

Hard

Used 373+ times

FREE Resource

AI

Enhance your content in a minute

Add similar questions
Adjust reading levels
Convert to real-world scenario
Translate activity
More...

20 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

The output of an exclusive-NOR gate is 1,Which input combination is correct?

A = 1 B = 0

A = 0 B = 1

A = 0 B = 0

none of the above

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

How many AND gates are required to implement the Boolean expression?

1

2

3

4

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In an SR latch built from NOR gates which condition is not allowed?

S=0, R=0

S=0, R=1

S=1, R=0

S=1, R=1

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In the toggle mode a JK flip-flop has

J = 0, K = 0

J = 1, K = 1

J = 1, K = 1

J = 1, K = 0

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

If J = K (J and K are shorted) in a JK flip-flop, what circuit is made

SR Flip Flop

D Flip Flop

T Flip Flop

M S J K Flip Flop

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

How many clock pulses will be required to completely load serially a 5-bit shift register?

1

5

7

6

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

On a master-slave flip-flop, when is the master enabled?

when the gate is LOW

when the gate is HIGH

both of the above

neither of the above

Access all questions and much more by creating a free account

Create resources

Host any resource

Get auto-graded reports

Google

Continue with Google

Email

Continue with Email

Classlink

Continue with Classlink

Clever

Continue with Clever

or continue with

Microsoft

Microsoft

Apple

Apple

Others

Others

Already have an account?