1.1.2 Types of processor

Several CISC instructions may be equivalent to a single RISC instruction

• TRUE

• FALSE

CISC aims to improve processing time by increasing the number of instructions understood by the CPU in the instruction set.

• TRUE

• FALSE

CISC aims to use as few lines of assembly code as possible, even if more clock cycles are needed as a result.

• TRUE

• FALSE

RISC aims to improve processing speed by simplifying instructions so that one line takes one clock cycle.

• TRUE

• FALSE

RISC code may have fewer lines of code, but will take more processor time.

• TRUE

• FALSE

CISC code may have fewer lines of code, but will take more processor time.

• TRUE

• FALSE

RISC code may have more lines of code than the CISC equivalent

• TRUE

• FALSE

CISC code can better utilise pipe-lining as the time needed for each operation can be predicted.

• TRUE

• FALSE

RISC code can better utilise pipe-lining as the time needed for each operation can be predicted.

• TRUE

• FALSE

CISC processors...

• Are physically larger

• Are better at complex tasks

• Use more electricity than RISC

• Expect more work from the compiler to generate more code

• Not as good at pipelining