verilog HDL

Verilog is an

• Case Insensitive

• Case Sensitive

• Can't say

The full form of HDL is _________________

• Higher Descriptive Language

• Higher Definition Language

• Hardware Description Language

• High Descriptive Language

The full form of VHDL is _____________

• Very High Descriptive Language

• Verilog Hardware Description Language

• Variable Definition Language

• None of the Mentioned

The Verilog HDL code starts with the keyword_________

• always

• module

• endmodule

• items

The Verilog HDL code ends with the keyword_________

• always

• module

• keys

• endmodule

Different types of modelling in Verilog HDL are _____

• Gate level, Data flow and Behavioral

• data, case and type

• Gate, Logic and gates

• None

In behavioral modeling the keyword used is _______

• always

• become

• and

• or

The keyword used for multiplying two bits in the form of gates is __________

• AND

• Or

• and

• none

The symbol used for bitwise AND operation is _____

• and

• or

• $

• &

The symbol used for Logical AND operation is ______

• and

• or

• &&

• None