FLIP FLOP 2

An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate each. If both S and R inputs are set to one, the outputs will be

• a. Q and Q' both 1

• b. No change in circuit output

• c. Q and Q' both 0

• d. Q and Q' complementary to each other

Consider the circuit shown below. Which of the following statements is true?

• a. The circuit would hold the previous state for S = 0, R = 0.

• b. The circuit would hold the previous state for S = 0, R = 1.

• c. The circuit would hold the previous state for S = 1, R = 1.

• d. The circuit would never be able to hold the previous state under any condition

Which of the following statements is NOT correct?

• a. Race around condition occurs in a JK latch when both the inputs are one.

• b. A flip flop is used to store one bit information.

• c. A transparent latch is D-type flip-flop with enable (level triggered) in place of a clock.

• d. Master-slave configuration is used in flip-flop to store two bits information.

The logic function depicting the behavior of the complementary output of T flip-flop is given by

• a. Q’ = T XOR Q

• b. Q’ = T XNOR Q

• c. Q’ = T OR Q

• d. Q’ = T NOR Q

The logic function depicting the behaviour of the complementary output of JK flip-flop is given

by

• a. Q’ = J’Q’ + KQ

• b. Q’ = JQ’ + K’ Q

• c. Q’ = J’K’

• d. Q’ = J’K’ + Q

Which of the following statements is/are true?

• A flip-flop is a level-sensitive storage element.

• A latch is a level-sensitive storage element.

• A latch is triggered both at the positive as well as the negative edges of a clock.

• A combinational circuit is triggered either at the positive edge or at the negative edge of a clock.

In the excitation table for a J-K flip-flop, what do we have to apply on the J and K inputs to change the output value from 0 to 1?

• a. J = 1, K = X

• b. J = X, K = 0

• c. J = X, K = 1

• d. None of these

This  flip-flop transitions on

• the falling clock edge.
• the rising clock edge.
• high clock level.
• low clock level.

What signal activates this Preset input?

• 0
• 1
• Low clock level
• High clock level

Preset forces Q to

• 1
• 0
• Q'
• No change