Verilog HDL QUIZ

Hardware Description Languages support

• Sequential Constructs

• Concurrent Constructs

• Sequential and Concurrent Constructs

• None of the Above

S'h16a35, where S is the size of the Number. S=?

• 15

• 16

• 20

• None of the Above

Correct Negative Numbers are represented as follows

• 4'h-72

• -3d'4

• -2d'7

• 3'd-7

input dataBus[32:0];

assign dataBus = 32'h56xba231;

what is the values of dataBus[20:12]=

• 10111010

• x10111010

• xx10111010

• None of the Above

2K memory bits

• reg memoryBits[0:1024]

• reg [1:0] memoryBits[0:1024]

• reg memoryBits[0:2045]

• None of the Above

#100 $stop;

• This will suspend the simulation at time = 100

• This will terminate the simulation at time = 100

• Invalid Syntax

• None of the Above

$monitor task

• Monitors will produce the output when ever it get executed.

• Monitors the signals when its value changes

• Monitor will produce the output when the signals are the same as earlier

• None of the Above

Port Connection Rules

• input in lower module will be reg in top level module,

  Output in lower module will be wire in top level module

  Wire in lower module will be wire in top level module

• input in lower module will be wire in top level module,

  Output in lower module will be wire in top level module

  Wire in lower module will be wire in top level module

• input in lower module will be wire in top level module,

  Output in lower module will be reg in top level module

  Wire in lower module will be wire in top level module

• None of the Above

A Module instantiation in higher level module

• Module lowerModuleName and sequence of the currentModule signals

• lowerModuleName ModuleInstanceName followed by sequence of lowerModule Signals equivalent signals in current modules.

• Module lowerModuleName and sequence of the lowerModule Signals

• None of the Above