DPSD UNIT-2 MCQ

A full adder can be made out of

• two half adders

• two half adders and a OR gate

• two half adders and a NOT gate

• three half adders

Which device has one input and many outputs?

• Multiplexer

• Demultiplexer

• Counter

• Flip flop

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the (EN)'LOW input be LOW. What is the status of the Y output?

• LOW

• HIGH

• DON'T CARE

• Can't be determined

How many data select lines are required for selecting eight inputs?

• 1

• 2

• 3

• 4

A 2 bit binary multiplier can be implemented using

• 2 input ANDs only

• 2 input X-ORs and 4-input AND gates only

• Two (2) input NORs and one XNOR gate

• XOR gates and shift registers

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

• A > B = 1, A < B = 0, A < B = 1

• A > B = 0, A < B = 1, A = B = 0

• A > B = 1, A < B = 0, A = B = 0

• A > B = 0, A < B = 1, A = B = 1

Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output?

• S₄S₃S₂S₁ = 0111, C_out = 0

• S₄S₃S₂S₁= 1111, C_out = 1

• S₄S₃S₂S₁= 1011, C_out = 1

• S₄S₃S₂S₁= 1100, C_out = 1

The logic function implemented by the circuit below is (ground implies a logic “0”)

• F = AND (P,Q)

• F = OR (P,Q)

• F = XNOR (P,Q)

• F = XOR (P,Q)

The Boolean function realized by the logic circuit shown is

• F = Ʃm (0,1,3,5,9,10.14)

• F = Ʃm (2,3,5,7,8,12.13)

• F = Ʃm (1,2,4,5,11,14.15)

• F = Ʃm (2,3,5,7,8,9.12)

A decoder can be used as a demultiplexer by ________.

• tying all enable pins LOW

• tying all data-select lines LOW

• tying all data-select lines HIGH

• using the input lines for data selection and an enable line for data input