ECE212_COmb2

The activity factor of the NAND gate

• is larger than that of the NOR gate

• is smaller than that of the NOR gate

• is equal to that of the NOR gate

The following does not affect the CMOS gates delay:

• fan in

• input pattern

• transistor sizing

• activity factor

To reduce the delay of a NAND gate

• make the bottom NMOS larger than the rest

• make the bottom NMOS smaller than the rest

• make the top NMOS larger than the rest

• make the top NMOS smaller than the rest

The parasitic delay of the 2-input NOR gate

• is equal to that of the 2-input NAND gate

• is smaller than that of the 2-input NAND gate

• is larger than that of the 2-input NAND gate

The logical effort depends on

• the input capacitance

• the output capacitance

• the supply

• the frequency