unit-1 LAYOUT RULES

Which of the following is a layout design rule?

• Minimum metal width
• Resistance value
• Maximum fanout
• Power dissipation

Which type of layer is used to define the interconnect in the layout design?

• Metal layers
• Diffusion layers
• Active layers
• Polysilicon layers

Which of the following design rules describes the minimum distance between two adjacent metal wires?

• Metal spacing
• Via enclosure
• Poly to poly spacing
• Contact to contact spacing

What is the minimum space required between two metal lines, if the minimum width of a metal line is 2 µm and the space is 1 µm?

• 1 µm
• 2 µm
• 3 µm
• 4 µm

Which of the following is not a common layout design rule?

• Minimum metal length
• Minimum area of the contact
• Minimum contact spacing
• Minimum metal spacing

Which type of layout design rule ensures that the metal lines have no sharp bends or corners?

• Minimum metal length and width
• Metal enclosure
• Minimum metal spacing
• Maximum metal width

What is the spacing required between two adjacent vias?

• Via spacing
• Metal spacing
• Contact spacing
• Poly to poly spacing

Which of the following is NOT a design rule for a CMOS layout design?

• Minimum width of the gate
• Minimum spacing between adjacent contacts
• Minimum spacing between adjacent metal layers
• Maximum length of the gate

What is the purpose of the contact layer in a CMOS layout design?

• To make electrical connections between layers
• To define the active area of the device
• To define the diffusion region of the device
• To define the location of vias

What is the minimum spacing between two adjacent metal layers in a CMOS layout design?

• 0.18 μm
• 0.25 μm
• 0.5 μm
• 1.0 μm