9618 15.1 RISC/CISC and Assembly

Several CISC instructions may be equivalent to a single RISC instruction

• TRUE

• FALSE

CISC aims to use as few lines of assembly code as possible, even if more clock cycles are needed as a result.

• TRUE

• FALSE

RISC aims to improve processing speed by simplifying instructions so that one line takes one clock cycle.

• TRUE

• FALSE

RISC code may have more lines of code than the CISC equivalent

• TRUE

• FALSE

Pipelining means...

• The fetch-decode-execute cycle runs more efficiently

• A full fetch-decode-execute cycle must complete before starting the next

• The next instruction is fetched while the previous instruction is still decoding

• CISC processors can run more efficiently

• RISC processors can run more efficiently

The instruction LDI loads a value into ACC using indirect addressing. Based on the contents of the registers and memory, what value will be loaded into the ACC as a result of the instruction LDI 45?

The instruction LDX uses indexed addressing to load a value into the ACC. Based on the content of the registers and memory, write an instruction that would load the number 52 into the ACC. You can only use LDX.

There are ​ (a)   stages of processing an instruction. It takes one instruction five clock cycles to pass through all stages. Without pipelining, it would take ​ (b)   cycles to execute four instructions. With pipelining, this can be improved to just ​ (c)   cycles. Pipelining is normally only available on ​ (d)   processors.

• 5
• 20
• 8
• RISC
• 4
• 25
• 15
• 30
• 10
• CISC

Draw logarithmic time complexity

Match the following OOP terminology to the correct example

• ClassA has an attribute of type ClassB.

• Encapsulation

• ClassA receives all attributes and methods of ClassB.

• Containment
• Access to attributes and methods can be limited and controlled by the programmer.

• Polymorphism

• MethodA has the ability to behave differently in different situations.

• Inheritance