COMBINATIONAL CMOS CIRCUIT

Choose the Active Low device

• NMOS

• PMOS

• CMOS

• BJT

The Image shows the cross section of ________

• NPN Transistor

• PNP Transistor

• NMOS Transistor

• PMOS Transistor

_______ produce "Strong Zero" output.

• NMOS

• PMOS

• CMOS

• INVERTER

The output of the Timing Diagram shows _____

• Degraded 1

• Degraded 0

• Active High

• Active Low

The picture shows the block diagram of static complementary CMOS. The X is _______

• VCC

• PDN

• PUN

• GND

In a static CMOS circuit, why the PMOS transistor located in Pull Up Network (tie to the VDD)?

• The PMOS transistor is active High

• The PMOS transistor is active Low

• The PMOS transistor is produce 'Strong One' output

• The PMOS transistor is produce 'Strong Zero' output

The transistor logic circuit in picture is a __________ circuit.

• NOR

• NAND

• NOT

• AND

The simplification of the Boolean equation in the picture may be using ____________ Law

• Absorption

• De Morgan's

• Double Complement

• Inverse

To draw the static CMOS logic circuit, the procedure below must follow:

• Determination of Series-Parallel Circuit from equation, Simplification PUN, Simplification PDN, Drawing the Circuit

• Simplification PUN, Simplification PDN, Drawing the Circuit, Determination of Series-Parallel Circuit from equation

• Simplification PUN, Simplification PDN, Determination of Series-Parallel Circuit from equation, Drawing the Circuit

• Determination of Series-Parallel from equation, Simplification PDN, Simplification PUN, Circuit, Drawing the Circuit

The correct equation for the transistors arrangement in the picture is ____

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