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QUIZ-1

Authored by RAVI KUMAR SARIKI

Education

University

10 Questions

Used 4+ times

QUIZ-1
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1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which among the following is a process of transforming RTL to a gate-level netlist?

Simulation

Optimization

Synthesis

Verification

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Media Image

The output of the following logic =?

logic 0

logic 1

x

z

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

#40 $finish indicates

End of simulation time

End of simulation at 40-time units

Suspend simulation at 40-time units

 

None

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Media Image

The output of the following logic =?

Logic 0

Logic 1

X

 

Z

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which model uses transistors as their basic components?

Switch level

Gate Level

Behavioral

Layout Level

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the default value of the reg data type?

0

1

x

z

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the time period of clock #20 clock = ~clock?

10

20

40

80

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