Pipelining in RISC V and MIPS

Technique for implementing parallelism that is transparent to the programmer

How often do instructions exit (instructions per time)

• Throughput

• Latency

• CPI

• Clock Okey

Registers that ensure there is no overlap and have the name of the stages they connect

• Instruction Registers

• Memory Registers

• Pipeline Registers

• ALUout

What is the most advanced method of branch prediction

• Predicted Taken

• Predicted not Taken

• 1-Bit Dynamic branch prediction

• 2-Bit Dynamic branch prediction

Most common data hazard

• RAW

• WAR

• WAW

• Structural