IHDL_Finals Quiz

What is the purpose of switch level modeling in Verilog?

• To provide support for transistor level modeling

• To model hardware structures using transistor models with analog input and output signal values

• To describe the interconnection of transmission gates

• To control the simulation and manipulate variables of the data types

What are the values carried by the interconnections in switch level modeling referred to as?

• Analog voltages

• Continuous values

• Signal strengths

• Digital values

Which keyword is used to model NMOS transistors in Verilog?

• ncontrol

• tranif0

• tran

• nmos

What is the purpose of a bidirectional switch in Verilog?

• To retain strength levels of signals from input to output

• To reduce signal strengths

• To conduct in both directions

• To conduct from drain to source

What type of procedural statement is used for updating integer, reg, time, and memory variables in Verilog?

• Continuous assignment

• Non-blocking assignment

• Procedural assignment

• Behavioral modeling

What is the purpose of a non-blocking procedural assignment in Verilog?

• To execute a statement a fixed number of times

• To control the execution of a statement until an expression becomes false

• To schedule assignments without blocking the procedural flow

• To execute before other statements in a sequential block

What is the behavior of posedge and negedge for unknown expression values in Verilog?

• Both are detected on the transition from 1 to unknown and from unknown to 0

• Both are detected on the transition from 0 to unknown and from unknown to 1

• Posedge is detected on the transition from 1 to unknown and from unknown to 0, negedge is detected on the transition from 0 to unknown and from unknown to 1

• Posedge is detected on the transition from 0 to unknown and from unknown to 1, negedge is detected on the transition from 1 to unknown and from unknown to 0

What is the purpose of the case statement in Verilog?

• To execute a statement until an expression becomes false

• To decide whether a statement is executed

• To test whether an expression matches several other expressions and branch accordingly

• To control the execution of a statement a fixed number of times

Which type of procedural statement is used to control the execution of a statement until an expression becomes false in Verilog?

• For

• While

• Repeat

• Forever

What are the procedures specified within in Verilog?

• Function

• Task

• Always blocks

• Initial blocks