Verilog TCL Quiz

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Education
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Professional Development
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Hard
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21 questions
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1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What is the default value for reg data type
0
1
x
d
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In continuous assignment left hand side must be
Net
Reg
Scalar or Vector Net
Scalar or Vector Net
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
If x=4 b1100 then x<<2 is
4 b1000
4 b0000
4 b0011
4 b0110
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
#40 $finish indicates
end of simulation time
end of simulation after 40 time units
suspend simulation at 40 time units
delay for 40 time units and then execute next line after $finish
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What do you mean by logic synthesis?
RTL description is converted in terms of logic gates by the use of synthesis tool
RTL description is simulated and the simulation waveforms are shown by synthesis tools
RTL description is remodelled from behavioural to data flow modelling by synthesis tools
RTL description is checked for any errors by synthesis tools
6.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
what is the correct set of Verilog code to swap contents of two register with and without temporary registers.
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What is wrong with following piece of code
Nothing wrong
incorrect a and b can overflow as it is incremented in an infinite loop
Simulation may not advance since forever doesn't have any timing control
A forever block cannot be used inside an initial block
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