
COA G13 15th April 2024
Authored by Jatin Arora
Computers
University
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15 questions
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1.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
The speed improvement formula expresses by Amdahl's Law is
Speedup = 1 / ((1 - P) * (P / S))
Speedup = 1 / ((1 - P) + (P / S))
Speedup = 1 / ((1 + P) + (P / S))
Speedup = 1 / ((1 - P) - (P / S))
2.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
The speedup of pipeline processing over a non pipeline processing is defined by the ratio
ntn / ((k + n -1 ) tp )
ntn / ((k -1 ) tp )
ntn / ((k + n +1 ) tp )
ntn / ((k - n -1 ) tp )
3.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
Assume a pipeline system has 4 segment will take ______ clock cycles to execute 100 tasks.
103
4.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
The correct ordering Arithmetic Pipeline segments are
1. Compare the exponents.
2. Align Mantissa.
3. Add or subtract the Mantissa.
4. Normalize the result.
1. Compare the exponents.
2. Add or subtract the Mantissa.
3. Align Mantissa.
4. Normalize the result.
1. Normalize the result.
2. Compare the exponents.
3. Add or subtract the Mantissa.
4. Align Mantissa.
1. Compare the exponents.
2. Add or subtract the Mantissa.
3. Normalize the result.
4. Align Mantissa.
5.
MULTIPLE SELECT QUESTION
20 sec • 1 pt
Pipelined processors are best classified into which one of the following Flynn's classifications of computers? (Multiple Options may correct)
6.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
The time delay of 4 segment pipeline are as t1= 50ns, t2= 30ns, t3= 95ns, and t4= 45ns. The interface register delay time tr is 5ns. What would be the recommended clock cycle time, tp?
50ns
30ns
95ns
100ns
7.
MULTIPLE CHOICE QUESTION
20 sec • 1 pt
In which of the following mechanisms, the interrupting device provides the address of the interrupt service routine (ISR)?
Hardware Interrupt
Software Interrupt
Vectored Interrupt
Daisy Chaining
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