CS2810 Review Unit 3

For this single-cycle processor, how long would it take for a load word instruction to finish processing (don't include the time it will take to write back to the register file)?

• 140

• 145

• 150

• 135

In a single-cycle processor, how many cycles does it take to execute a branch instruction?

• 1

• 2

• 3

• 4

Which of the following are true for a single-cycle processor?

• The clock cycle is as slow as the slowest instruction

• The clock cycle is as slow as the slowest instruction stage

• The clock cycle is not used for a single-cycle processor

• Each instruction stage takes a single clock cycle to complete

Which of the following is a benefit of pipelined processors?

• Increased clock cycle time

• Increased instruction throughput

• Simplified control logic

• Reduced power consumption

In a pipelined MIPS processor, which stage is responsible for updating the program counter (PC)?

• Instruction Fetch

• Instruction Decode

• Execute

• Writeback

In a pipelined MIPS processor, which of the following can cause a control hazard?

• Data dependencies between instructions

• Branch instructions

• Memory access delays

• Register file conflicts

Which pipelining stage is responsible for reading the register file?

• Instruction Fetch

• Instruction Decode

• Execute

• Memory Access

• Register File Write Back

In a pipelined MIPS processor, what is the purpose of the pipeline registers?

• To store the results of each pipeline stage

• To hold the instructions waiting to be executed

• To store data in case we need to stall

• 1. To resolve control hazards

In a pipelined MIPS processor, what happens when a data hazard is detected?

• The pipeline is stalled until the hazard is resolved

• The instruction causing the hazard is discarded

• The processor switches to a different thread

• The register file is updated immediately

The following MIPS snippet is an example of _____
beq $t0, $t1, label

add $s0, $s1, $s2

label:

sub $s3, $s4, $s5

• a control hazard

• a data hazard

• a double-pumped register file

• None of the Above