CPE382 Final Exam

What is Verilog?

• A programming language for hardware description

• A high-level programming language for software development

• A data visualization tool

• An operating system

Which of the following represents a hardware component in Verilog?

• Module

• Function

• Loop

• Variable

In Verilog, what is the purpose of the "always" block?

• To declare variables

• To instantiates modules

• To specify simulation time

• To describe behavior using procedural statements

What is the purpose of posedge keyword in Verilog?

• To specify a positive edge-triggered flipflop

• To specify the negative edge-triggered flip-flop

• To specify a synchronous reset

• To specify an asynchronous reset

How are multi-bit signals represented in Verilog?

• As an array of bits.

• As separate single-bit signals.

• As string of characters.

• As floating-point number.

How is a Verilog testbench used?

• To synthesize hardware designs

• To simulate and verify hardware designs

• To debug software programs

• To measure clock frequency

Which RTL description style uses Boolean equations to model

combinational logic?

• Behavioral

• Dataflow

• Structural

• Register transfer

Which one of the following keywords is used for a non-blocking

assignment in Verilog?

• =

• <=

• ->

• ==>

What is the purpose of the “initial” block in Verilog?

• To define the primary clock

• To initialize variables at the beginning of the simulation

• To specify timing constraints

• To define a counter

How are delays specified in a Verilog simulation?

• delay keyword

• using a separate delay module

• using the "#" symbol

• using the "@" symbol