pahc 5.1

pahc 5.1

University

•

50 Qs

quiz-placeholder

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pahc 5.1

pahc 5.1

Assessment

Quiz

•

Computers

•

University

•

Practice Problem

•

Easy

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50 questions

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1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Given a computer with main memory capacity of 256MB, Cache memory capacity of 64KB, Line size of 64bytes, memory compartment length of 4bytes. In the case of the direct mapping technique of the Tag + Line + Word address format emitted by the processor to access the Cache is:

[<$>] 11+11+5

[<$>] 12+11+4

[<$>] 12+12+3

[<$>] 11+12+4

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

With an SRAM memory chip with a 24-line address bus and an 8-line data bus, what is the maximum capacity of memory management?

[<$>] 32 MegaBytes

[<$>] 8 MegaBytes

[<$>] 64 MegaBytes

[<$>] 16 MegaBytes

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In the 2 N × M memory structure , which of the following statements is correct?

[<$>] Memory includes 2^ N memory words and M memory modules

[<$>] Memory consists of 2^ N memory cells, each memory cell contains M bits

[<$>] Memory includes 2^ N Bytes and M memory modules

[<$>] Memory includes 2^ N memory words and M memory modules

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Given a computer with main memory capacity of 4GB, cache memory capacity of 512KB, line size of 32bytes, memory compartment length of 1 byte. In the case of the direct mapping technique of the Tag + Line + Word address format emitted by the processor to access the Cache is:

[<$>] 13+5+14

[<$>] 5+14+13

[<$>] 14+13+5

[<$>] 13+14+5

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Cache memory works thanks to the principle:

[<$>] Operating principles of computers

[<$>] Data recording control principle

[<$>] Localize memory reference

[<$>] Principle of controlling data reading

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

With a SRAM memory chip with n address lines and m data lines, the capacity of the chip is:

[<$>] 2 m xn bytes                      

[<$>] 2 n xm bytes      

[<$>] 2 m xn bits                         

[<$>] 2 n xm bits    

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Considering Cache memory, which of the following address mapping techniques are there?

[<$>] Direct, full link, aggregate link

[<$>] Direct, continuous link, intermittent link

[<$>] Collection link, element link, union link

[<$>] Direct, indirect, combined

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