PD FLOW

Which files could be an input of Floorplan?

• Netlist (.v)
• SDC (.tcl or .sdc)
• UPF
• DEF

Which shapes of chip could be if the aspect ratio is not 1?

• Square
• Regtangle
• Rectilinear
• Circle

If the core utilization is 0.7, it means:

• 70% area is available for placement of cells
• 70% area is available for routing
• 70% cells will be able to be placed in the core area
• 70% nets will be able to be routed

Which factors could affect to the placement of macros?

• Fly-line analysis
• Data-flow diagram
• Design module hierarchy
• Channel length calculation

Which blockages allow buffers & inverters placement inside?

• Hard blockage
• Soft blockage
• Partial blockage
• Virtual blockage

What is the order of power flow (from outside to inside of chip)?

• Pads > Stripes > Rings > Rails > Standard cells
• Pads > Rails > Stripes > Rings > Standard cells
• Pads > Rails > Rings > Stripes > Standard cells
• Pads > Rings > Stripes > Rails > Standard cells

Which physical cells could prevent latch-up phenomenon?

• Filler cells
• Decap cells
• Tap cells
• Tie cells

Floorplan qualification includes:

• All macros should be placed and fixed
• All IO pins must be placed and fixed
• No macro overlap
• All are correct

What should we NOT do at placement?

• Place the standard cells
• Optimize design
• Place macros
• Place ports

What are the objectives of Placement?

• Timing, Power, Area optimization
• Minimum cell density
• Routable design
• Minimum timing DRC