Computer Architecture and Virtual Machines Quiz

What is the primary purpose of a control unit in a CPU?

• To perform arithmetic calculations

• To ensure machine instructions are handled correctly

• To manage memory allocation

• To store data permanently

Which of the following describes CISC architectures?

• Emphasizes a rich set of complex instructions

• Prioritizes a simpler set of instructions

• Requires minimal loading of data from memory

• Uses fixed-length instructions

What does RISC stand for?

• Random Instruction Set Computing

• Reduced Instruction Set Computing

• Rapid Instruction Set Computing

• Repetitive Instruction Set Computing

Which of the following is a characteristic of RISC processors?

• Variable length instructions

• Fewer instructions

• More addressing modes

• More complex instructions

What is pipelining in the context of RISC architectures?

• A way to reduce the number of registers

• A process that slows down instruction execution

• A method to increase instruction complexity

• A technique to execute multiple instructions simultaneously

What is the Fetch Decode Execute Cycle?

• A programming language

• A type of computer architecture

• A sequence of steps in instruction processing

• A method for data storage

What is a virtual machine?

• A software-based emulation of a physical computer

• A physical computer

• A hardware component

• A type of operating system

Which of the following is an advantage of using virtual machines?

• Increased hardware costs

• Ability to run multiple operating systems

• Reduced software compatibility

• Slower performance

What does ISA stand for?

• Integrated System Architecture

• Instructional Software Application

• Instruction Set Architecture

• Internal Software Architecture

What is the main difference between CISC and RISC?

• RISC uses variable length instructions while CISC uses fixed length

• CISC emphasizes complex instructions while RISC emphasizes simplicity

• RISC has more complex instructions than CISC

• CISC has fewer instructions than RISC