ECE625 Chapter16C

What types of dependencies arise due to out-of-order instruction issuing and completion?

• RAW dependencies and resource conflicts

• WAW dependencies and WAR dependencies

• RAW and WAW dependencies

• Resource conflicts and data hazards

Which of the following techniques is used to avoid conflicts caused by WAW and WAR dependencies in superscalar processors?

• Branch Prediction

• Register Renaming

• Scoreboarding

• Pipelining

How does register renaming resolve storage conflicts?

• By allocating hardware registers dynamically to hold new values

• By stalling the pipeline until the conflict is resolved

• By duplicating functional units

• By discarding conflicting instructions

Which hardware technique is NOT primarily responsible for improving machine parallelism in a superscalar processor?

• Out-of-order issue

• Register renaming

• Pipelined functional units

• Static scheduling

What is the role of the instruction window in a superscalar processor?

• To control the flow of instructions into the pipeline

• To fetch branch target instructions only

• To allow the processor to look ahead and find independent instructions

• To execute instructions out-of-order

Which of the following is NOT a benefit of register renaming?

• Resolving WAR and WAW dependencies

• Increasing pipeline performance by removing antidependencies

• Eliminating RAW dependencies

• Improving instruction issue flexibility

Which branch prediction technique uses a branch history analysis for dynamic prediction?

• Static branch prediction

• Delayed branch strategy

• Dynamic branch prediction

• Prefetching branch target instructions

Why is the delayed branch strategy less appealing in superscalar machines?

• Because multiple instructions need to execute in the delay slot, raising dependency issues

• Because it requires dynamic branch prediction

• Because it does not allow out-of-order execution

• Because it increases structural hazards

What is the final step in superscalar execution of programs, where instructions are made permanent?

• Fetching instructions

• Register renaming

• Speculative execution

• Committing or retiring the instruction

Which of the following is a key element of superscalar processor hardware?

• Static scheduling logic

• Single instruction issue per cycle

• Multiple instruction fetch and decode stages

• Sequential instruction completion only