3.1.1 Sequential Logic Flip/Flops

Discuss how the transparent D-latch differs from other flip-flops.

What happens to the output Q when J=0, K=0, and CLK is at the rising edge?

• No Change

• Clear

• Set

• Toggle

In a Positive Edge Triggered J/K flip-flop, when J=0, K=0, and CLK is at the rising edge, the output Q is (a)   .

• 0

• 1

• Q0'

• Q0

The flip-flop's CLOCK input is ______ sensitive, meaning the flip-flop's output changes on the ______ (rising or falling) of the CLOCK input.

(a)  

What is the primary function of the 74LS76 as described in the image?

Fill in the blank: The configuration is nonstable when either the preset and/or clear inputs return to their inactive ( (a)   ) level.