UVM and SystemVerilog Quiz

What is the primary purpose of the UVM factory?

• To create clocking mechanisms

• To automate sequence generation

• To enable dynamic and configurable object creation

• To store and forward transactions

In UVM, which component is responsible for converting a sequence item into signals?

• Monitor

• Driver

• Sequencer

• Environment

Which method is used to raise an objection in UVM?

• raise_phase_objection()

• phase.raise_objection()

• raise_objection()

• phase.objection_raise()

What does the uvm_config_db do in UVM?

• Passes configuration information to specific components

• Stores testbench logs

• Handles transaction recording

• Controls UVM phases

How is a virtual sequence typically started?

• By calling start() directly on the sequence

• By using a sequencer pointer in the test class

• By defining it in the UVM monitor

• By overriding the factory default

Which of the following is NOT true about initial blocks in SystemVerilog?

• They execute once at time 0.

• Multiple initial blocks execute concurrently.

• They can be used to drive clock signals.

• They cannot contain delays.

What is the primary difference between interface and module in SystemVerilog?

• An interface cannot contain tasks and functions.

• An interface is used to group signals and simplify connections.

• A module is used only in testbenches.

• Interfaces can directly instantiate hardware.

In SystemVerilog, what does the keyword unique ensure in a case statement?

• No two cases overlap.

• All cases must execute sequentially.

• The case is evaluated as a priority encoder.

• There is exactly one matching case at runtime.

What is the role of the covergroup in SystemVerilog?

• To assert design functionality

• To perform code coverage

• To measure functional coverage

• To generate random data

How is logic different from reg in SystemVerilog?

• logic is purely synthesizable, whereas reg is not.

• logic can be used for multi-driver signals, unlike reg.

• logic is a 4-state data type, whereas reg is only 2-state.

• logic is the preferred replacement for reg in modern designs.