Computer Architecture Quiz

In a typical micro-operation implementation, the arithmetic logic shift unit (ALSU) combines multiple functionalities. Consider a scenario where an ALSU receives three control signals: C1, C2, and C3. If C1=1, the unit performs an addition operation. If C2=1, it executes a logical AND. If C3=1, it performs a shift operation. For C1=1, C2=0, and C3=1, which of the following describes the sequence of operations executed?

• Logical AND operation followed by a shift operation

• Addition operation followed by a shift operation

• Logical AND operation followed by an addition operation

• Shift operation followed by an addition operation

In a bus system where multiple registers share a common data bus, data transfer between two registers involves specific control signals. If the control lines S0, S1 are used to select the source register and T0, T1 are used for the destination register, what is the minimum number of multiplexers and decoders required for a system with 8 registers?

• 2 multiplexers and 1 decoder

• 1 multiplexer and 2 decoders

• 3 multiplexers and 1 decoder

• 1 multiplexer and 1 decoder

In a CPU design, the instruction cycle comprises multiple phases, including fetch, decode, execute, and write-back. If an instruction involves both memory-reference operations and an indirect addressing mode, which additional phase is required in the instruction cycle, and why?

• A memory fetch phase to retrieve the operand from the specified address.

• An indirect phase to resolve the effective address of the operand.

• An execution phase to perform a logical operation before the operand fetch.

• A write-back phase to store the effective address in the register.

A general register organization in a CPU has 16 registers with 4 addressing modes. If an instruction format includes a 4-bit opcode, a 4-bit register address, and 2 bits for the addressing mode, what is the total number of unique instructions possible in this system?

• 64

• 256

• 1024

• 2048

In a system where data transfer occurs between registers through a common bus, the control signal determines the active source and destination registers. If there are 32 registers, and each register has a 16-bit width, how many selection lines are required for the multiplexer and decoder to manage the bus?

• 4 for the multiplexer, 4 for the decoder

• 5 for the multiplexer, 5 for the decoder

• 6 for the multiplexer, 5 for the decoder

• 5 for the multiplexer, 4 for the decoder

Shift micro-operations are used to manipulate data within registers. Consider a right arithmetic shift applied to an 8-bit signed binary number 10110110. What will the content of the register be after two consecutive shifts?

• 11101101

• 10111101

• 11111011

• 00101101

A computer performs an addition of two 8-bit binary numbers using arithmetic micro-operations. The first number is 11010110, and the second number is 01101011. If an overflow occurs, how is it detected in the result?

• By examining the carry bit generated from the MSB addition

• By comparing the carry-in and carry-out of the sign bit

• By checking the sum bits of the higher nibble

• By inspecting the parity bit of the result

In a CPU with memory-reference instructions, the opcode 111 corresponds to a specific operation. If the addressing mode used is indirect, which of the following sequences best describes the phases involved in executing the instruction?

• Fetch, Decode, Direct Access, Execute

• Fetch, Decode, Indirect Access, Execute

• Fetch, Decode, Execute, Write-back

• Fetch, Decode, Register Transfer, Execute

A CPU uses a stack organization to evaluate expressions. Given the postfix expression AB+C*D−, where A=4, B=5, C=6, and D=2, what is the final value stored in the stack after the complete evaluation?

• 26

• 16

• 20

• 14

In a CPU with a stack organization, the following sequence of instructions is executed: PUSH 5, PUSH 10, ADD, PUSH 8, MULTIPLY. What will be the value on the top of the stack after the above instructions are executed?

• 120

• 130

• 40

• 150