Quiz-1

The -------------- of a logic gate e.g. inverter is the difference in time (calculated at 50% of input-output transition), when output switches, after the application of input

• data delay

• propagation delay

• inertial delay

• transport delay

-- is the time, during transition, when output switches from 10% to 90% of the maximum value.

• Transient time

• OFF time

• Delay time

• Rise time

--is the time, during transition, when output switches from 90% to 10% of the maximum value.

• Fall time

• Rise time

• Delay time

• Cycle time

Digital logic implementations exhibit finite rise and fall delays and finite propagation times due to -------- associated with the gates.

• CMOS inverter delay

• switched capacitor circuits

• inductance and reactance

• capacitances and resistances

--is the time between identical points of successive cycles in the signal waveform

• Cycle time

• ON time

• OFF time

• Delay time