Verilog HDL -module 1 Quiz

Full of HDL is.......and two HDL Languages are ........and ..................

• Hardware developed language

  VHLD

  Verilog

• Hardware debugging language

  Verilag HDL

  VHDL

• Hardware description
  Language

  Verilog

  C
  

• Hardware description
  Language

  Verilog

  VHDL

Correct order of HDL based design flow is..

• implementation->

  sysnthesis->

  RTL description->

  Design specification

• RTL description->

  Design specification->

  implementation->

  sysnthesis

• Design specification

  RTL description->

  sysnthesis->

  implementation

• Design specification

  RTL description->

  implementation->

  sysnthesis

which among the following are related to importance of HDL?

a) Designers can be described at a very abstract level by use of HDL.

b) Designers can write their RTL description by choosing certainfab technology.

c) Easier way to develop and debug digital circuits.

d) Similar in syntax to Python programming

• a,b

• a,b,c

• a,b,c,d

• a alone

Hierarchical modelling concepts are ......and ........... also cells that cannot further be divided is called ......

• Top up

  bottom down

  leef cells

• Top up

  bottom up

  leefy cells

• Top down

  bottom up

  leef cells

• Top down

  bottom up

  leaf cells

Highest level of abstraction provided by Verilog HDL is?

• Behavioural

• Gate level

• Data flow

• structural

The process of creating objects from a module template is called....

• Test bench

• stimulus.

• Instantiation

• system tasks

The functionality of the design block can be tested by applying .............and checking results.

• a) Stimulus

• b) Compiler directives

• c) Testbench

• d) both a and c

Describe the structure of a testbench in Verilog.

• A testbench in Verilog does not need to instantiate the DUT.

• A testbench in Verilog consists only of a module declaration and no signal declarations.

• A testbench in Verilog includes a module declaration, signal declarations, instantiation of the DUT, initial and always blocks for stimulus and monitoring, and simulation control.

• A testbench requires only a single always block for stimulus and monitoring.

#40 in verilog indicates

• 40ms time

• 40us time.

• 40ns time.

• 40s time

Given below are lexical conventions in verilog except

• registers

• whitespace

• comments

• Identifiers