CAO-Unit-1

In Register Transfer Language (RTL), what does MAR stand for?

• a) Memory Allocation Register
  
  
  

• b) Memory Address Register

• c) Machine Access Register

• d) Main Arithmetic Register

In which addressing mode is the operand specified directly within the instruction?

• a) Indirect Addressing

• b) Register Addressing

• c) Direct Addressing

• d) Immediate Addressing

Which register holds the address of the next instruction to be fetched?

• a) IR (Instruction Register)

• b) AR (Address Register)

• c) PC (Program Counter)

• d) SC (Sequence Counter)

Which of the following is checked first during the decode phase?

• a) Whether the instruction is a memory reference or register instruction

• b) Whether the instruction is indirect or direct

• c) Whether the instruction is an I/O instruction

• d) Whether the instruction is valid

Which of the following best describes displacement addressing mode?

• a) The operand is stored in a register

• b) The effective address is computed using a base address and an offset

• c) The operand is stored in memory with its address directly specified in the instruction

• d) The operand is stored within the instruction itself

Which of the following operations is equivalent to an arithmetic right shift of 1 bit?

• a) Division by 2

• b) Multiplication by 2

• c) Addition with a shifted version of the number

• d) Bitwise AND with a mask

What is the result of performing an arithmetic right shift on 11110100 by 1 bit?

• a) 01111010

• b) 11111010

• c) 01110100

• d) 11110110

• If the 8-bit two’s complement number 01011010 is shifted left by 1, what will be the new binary value?
  
  
  
  
  

• • a) 10110100

• • b) 10111000

• • c) 01011000

• • d) 00101100

Which RTL statement correctly represents an indirect addressing mode?

• a) R1 ← M[AR]

• b) AR ← M[AR]

• c) R1 ← M[M[AR]]

• d) PC ← PC + 1

Which of the following operations is commonly performed during the fetch cycle in RTL?

• a) PC ← PC + 1, IR ← M[PC]

• b) R1 ← R2 + R3

• 
  c) MAR ← M[IR]

• 
  d) M[PC] ← IR