Computer Organization And Architecture Quiz Part1

Computer Organization And Architecture Quiz Part1

University

29 Qs

quiz-placeholder

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Computer Organization And Architecture Quiz Part1

Computer Organization And Architecture Quiz Part1

Assessment

Quiz

Computers

University

Hard

Created by

Comprehensive Viva

FREE Resource

29 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

1 min • 1 pt

Match the following.

(a) Immediate address mode                (1) Local variables

(b) Direct address mode                       (2) Relocatable programs

(c) Indirect address mode                     (3) Pointer

(d) Index addressing mode                   (4) Locality of reference

(e) Base address mode                          (5) Arrays

(f) Relative address mode                     (6) Constant Operands

a6 b1 c3 d5 e2 f4

a5 b4 c6 d3 e1 f2

a3 b5 c2 d4 e1 f2

a6 b5 c2 d3 e1 f4

2.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Register renaming is done in pipelined processors_______.

as an alternative to register allocation at compile time

for efficient access to function parameters and local variables

to handle certain kinds of hazards

as part of address translation

3.

MULTIPLE CHOICE QUESTION

1 min • 1 pt

The amount of ROM needed to implement a 4-bit multiplier is

64 bits

128 bits

1Kbits

2Kbits

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Memory interleaving is done to

Increase the amount of logical memory

Reduce memory access time

Simplify memory interfacing

Reduce page faults

5.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

before effective address calculation has started

during effective address calculation

after effective address calculation has completed

after data cache lookup has completed

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

The main virtue for using single Bus structure is ____________

Fast data transfers

Cost effective connectivity and speed

Cost effective connectivity and ease of attaching peripheral devices

None of the mentioned

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Memory Buffer Register (MBR) is connected to ___.

Control Bus

Address Bus

Data Bus

System Bus

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