Quiz about Lab Review 1

Question 1

Convert the following octal number to hexadecimal: 0o31415

Accepted Answer

0x330d

Answer

0x3104

Answer

0x230d

Answer

0x2304

Question 2

What is the ASCII string represented by the hexadecimal values 48 65 4C 4C 6F?

Accepted Answer

HeLLo

Answer

Hullo

Answer

Hello

Answer

HELLO

Question 3

What logic gate is represented by the circuit in the diagram?

Accepted Answer

and

Answer

or

Answer

xor

Answer

nor

Question 4

Converting 4.125 to an IEEE floating point number

Accepted Answer

0 10000001 00001000000000000000000

Answer

0 10000010 00001000000000000000000

Answer

0 10000001 00000100000000000000000

Answer

0 10000010 00000100000000000000000

Question 5

Given the following CircuitSim circuit, what will the value of OUT be when A=0, B=1, and C=1?

Accepted Answer

10

Answer

01

Answer

00

Answer

11

Question 6

Is this a valid grey code?

Accepted Answer

No

Answer

Yes

Question 7

12. What is an optimal grouping for the following K-Map?

Accepted Answer

Question 8

Given the following K-Map, what is the correct simplification?

Accepted Answer

B'D' + A'D' + ABC'D

Answer

A'B'D' + B'D' + ABC'D

Answer

A'D' +A'B'D' + ABC'D

Answer

B'D' + A'BD' + ABC'

Question 9

If a computer has $$2^{16}$$ memory locations and each memory location holds 1 byte, what is the addressability of the computer in bits?

Accepted Answer

8 bits

Answer

$$2^{16}$$ bits

Answer

$$2^{13}$$ bits

Answer

1 bit

Question 10

Which of the following is true?

Accepted Answer

Address space is the number of memory locations and addressability is the size of each memory location.

Answer

Address space is the total number of bytes we can store in memory and addressability is the size of each memory location.

Answer

Address space is the number of memory locations and addressability is the total number of bytes we can store in memory.

Answer

Address space is the size of each memory location and addressability is the number of memory locations.

Question 11

If we have an address space of 256 and our addressability is 16 bits, what is our total memory in bytes?

Accepted Answer

512 bytes

Answer

256 bytes

Answer

4096 bytes

Answer

128 bytes

Question 12

Given the following circuits, which one(s) use(s) sequential logic?

Accepted Answer

Accepted Answer

Question 13

Which of the following are edge triggered? Select all that apply.

Accepted Answer

D Flip Flops

Answer

RS Latches

Answer

Gated D Latch

Answer

Memory

Question 14

Which of the following is true?

Accepted Answer

Memory is made of gated D latches. Registers are made of D flip flops.

Answer

Memory is made of D flip flops. Registers are made of gated D latches.

Answer

Memory is made of only RS latches. Registers are made of gated D latches.

Answer

Memory is made of D flip flops. Registers are made of only RS latches.

Question 15

Is this circuit level or edge triggered?

Accepted Answer

Rising Edge Triggered

Answer

Level Triggered

Answer

Falling Edge Triggered

Question 16

What is the purpose of the tri-state buffer in the LC3?

Accepted Answer

To control access to the bus and prevent conflicts

Answer

To temporarily store data during instruction execution

Answer

To perform arithmetic operations between registers

Answer

To decode instruction opcodes for execution

Question 17

What is the IR, and what does it hold?

Accepted Answer

IR is the instruction register, and it holds the current instruction.

Answer

IR is the immediate register, and it holds the current instruction.

Answer

IR is the instruction register, and it holds the address of the next instruction.

Answer

IR is the immediate register, and it holds the address of the current instruction.

Question 18

What would the condition codes be set to after the following?

Accepted Answer

Z

Answer

P

Answer

N

Question 19

What gates and LD signals are asserted during 1st clock cycle of FETCH?

Accepted Answer

GatePC, LD.MAR

Answer

GateMDR, LD.MDR

Answer

GateMDR, LD.MAR

Answer

GatePC, LD.MDR

Question 20

What gates and LD signals are asserted during 3rd Clock Cycle of LDI?

Accepted Answer

Gate.MDR, LD.MAR

Answer

Gate.MAR, LD.MDR

Answer

Gate.ALU, LD.MDR

Answer

Gate.ALU, LD.MAR

Question 21

What gates and LD signals are asserted during 2nd Clock Cycle of ST?

Accepted Answer

Gate.ALU, LD.MDR

Answer

Gate.MAR, LD.MDR

Answer

Gate.MDR, LD.MAR

Answer

Gate.ALU, LD.MAR

Question 22

How many clock cycles does it take to run the LD, STI, JMP instruction sequentially (accounting for fetch and decode)?

Accepted Answer

21

Answer

9

Answer

18

Answer

23

Question 23

Given the following state machine, and a starting state of 00, which of the following sequences of outputs should we expect after the following transitions are taken?

p = 0, p = 1, p = 1, p = 0

Accepted Answer

0mph, 0mph, 5mph, 10 mph, 5mph

Answer

0mph, 0mph, 5mph, 5 mph, 0mph

Answer

0mph, 5mph, 10mph, 5 mph, 0mph

Answer

0mph, 5mph, 5mph, 10 mph, 5mph

Question 24

Convert the hex to an LC3 instruction: x5000

Accepted Answer

AND R0, R0, R0

Answer

AND R0, R0, #0

Answer

ADD R0, R0, #0

Answer

ADD R0, R0, R0

Question 25

Where do control signals come from?

Accepted Answer

Finite State Machine

Answer

Data Bus

Answer

Program Counter

Answer

Instruction Register

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