AHJN: Unit15-P2-Hardware

What is the primary advantage of RISC processors in terms of pipelining?

• They require fewer transistors

• They have more complex instructions

• They make pipelining function more easily

• They have more addressing modes

Which of the following is NOT a stage in the fetch-execute cycle?

• Instruction fetch

• Instruction decode

• Operand fetch

• Instruction encrypt

What is the main purpose of interrupts in a processor?

• To increase clock speed

• To handle external events and prioritize tasks

• To implement pipelining

• To reduce power consumption

In CISC architecture, what is the primary characteristic of instructions?

• They are always single-cycle

• They are of fixed length

• They can be multi-cycle and complex

• They are limited to basic arithmetic operations

Which of the following best describes the function of the address bus?

• It carries data between the CPU and memory

• It specifies the memory location for read/write operations

• It controls the flow of data in the system

• It synchronizes all computer operations

What is the primary advantage of increasing the address bus width from 16-bit to 64-bit?

• Faster data transfer

• More complex instructions

• Larger addressable memory space

• Reduced power consumption

Which of the following is NOT a typical characteristic of RISC processors?

• Fixed-length instructions

• Emphasis on hardware

• Fewer addressing modes

• Use of general-purpose registers

What is the main purpose of the clock in a processor?

• To keep track of time

• To synchronize operations

• To generate random numbers

• To control the temperature

In the context of parallel processing, what does VLIW stand for?

• Very Large Instruction Width

• Variable Length Instruction Word

• Very Long Instruction Word

• Virtual Logic Instruction Workflow

Which of the following best describes the function of the control bus?

• It carries data between components

• It specifies memory addresses

• It manages the flow of control signals

• It stores temporary data