Computer Architecture Quiz 2

Which component manages Direct Memory Access (DMA) transfers?

• CPU

• Device drivers

• DMA controller

• System bus

Asynchronous data transfer using "handshaking" ensures:

• Fixed clock synchronization

• Error-free transmission via control signals

• Higher data transfer rates than strobe pulses

• Priority-based interrupt handling

Which unit resolves interrupt priority conflicts?

• DMA controller

• Interrupt controller

• I/O processor

• System clock

Vector processors excel at:

• Handling conditional branches

• Single-threaded tasks

• Simultaneous operations on data arrays

• Low-latency I/O operations

In a 5-stage RISC pipeline (IF, ID, EX, MEM, WB), a data hazard occurs when:

• A branch instruction is mispredicted

• An instruction depends on the result of a previous instruction

• Two instructions access the same memory location

• The pipeline is fully utilized

Pipeline hazards caused by data dependencies are resolved using:

• Branch prediction

• Forwarding/bypassing

• Stalling

• Speculative execution

In memory-mapped I/O, which statement is true?

• I/O devices have a separate address space

• The I/O devices and memory share the same address space

• A dedicated memory segment is reserved for I/O

• I/O operations use a different bus

Which of the following is NOT a peripheral device?

• Keyboard

• Printer

• ALU

• Hard Disk

Serial communication is preferred over parallel communication for:

• Short distances

• Long distances

• High-speed data transfer

• Internal computer buses

Vector processors are most efficient for:

• Scalar operations

• Repetitive operations on large data sets

• Interrupt handling

• Branch instructions