Computer Architecture Quiz

A processor executes an instruction sequence where register transfers occur in the following order: 1. R1 ← R2 + R3 2. R4 ← R1 × R5 3. R6 ← R4 - R2 If register transfers are performed in a pipelined system, what kind of hazard is most likely to occur, and what technique can resolve it?

• Structural hazard; resolved using register renaming.

• Data hazard; resolved using forwarding (bypassing).

• Control hazard; resolved using branch prediction.

• Resource hazard; resolved using dynamic scheduling.

In a register transfer system, assume that a control unit generates the following micro-operations for an instruction: 1. MAR ← PC 2. MDR ← Memory[MAR] 3. IR ← MDR 4. PC ← PC + 1 5. Decode and execute Which of the following statements is true about this sequence?

• It represents a typical instruction fetch cycle.

• It represents an arithmetic instruction execution.

• It represents a memory write-back cycle.

• It represents a branch instruction execution.

A computer system has a single shared bus with multiple devices requesting memory access. The probability of a device needing access in one clock cycle is 0.4. If there are 4 devices, what is the probability that no device will need access in a given cycle?

• 0.1296

• 0.3456

• 0.8704

• 0.9216

In a system with a multiple-bus organization, increasing the number of buses results in:

• Lower data transfer rates due to increased contention.

• Improved performance but increased hardware complexity.

• Reduced instruction-level parallelism.

• Decreased memory bandwidth.

Consider a 5-stage pipeline (IF, ID, EX, MEM, WB). If a load instruction LW R2, 0(R1) is immediately followed by an ADD R3, R2, R4, which hazard occurs, and how can it be resolved?

• Structural hazard; resolved using separate ALU units.

• Data hazard; resolved using forwarding.

• Control hazard; resolved using branch prediction.

• Resource hazard; resolved using superscalar execution.

A pipelined processor has a CPI of 1.2 when branch mispredictions are ignored. If the branch misprediction rate is 5% and each misprediction causes a 3-cycle penalty, what is the new effective CPI?

• 1.35

• 1.40

• 1.15

• 1.25

A superscalar processor can issue 4 instructions per cycle. If the pipeline depth is 6 stages and there are 50% stall cycles, what is the effective instruction throughput (IPC)?

• 2.0

• 2.5

• 3.0

• 4.0

Consider an out-of-order processor executing the following instructions: 1. ADD R1, R2, R3 2. SUB R4, R1, R5 3. MUL R6, R4, R7 Which hazard can occur if instruction 3 executes before instruction 2, and how is it resolved?

• WAR hazard; resolved using register renaming.

• RAW hazard; resolved using forwarding.

• WAW hazard; resolved using dependency tracking.

• No hazard occurs.

Which mechanism is used in Tomasulo's Algorithm to ensure correct instruction commit order?

• Scoreboarding

• Register renaming

• Reorder buffer

• Pipeline flushing

A modern processor executes 128-bit SIMD instructions. If a scalar operation takes 4 cycles, how many cycles would a vectorized equivalent instruction take, assuming full utilization?

• 1

• 2

• 4

• 8