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CPU Architecture Quiz

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CPU Architecture Quiz
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102 questions

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1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which of the following best describes the concept of pipelining in CPU architecture?

It increases the clock speed of the processor

It allows multiple instructions to be executed simultaneously.

It enables direct data transfer between CPU registers and storage devices

It eliminates the need for instruction decoding

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the primary advantage of using a superscalar processor?

It reduces power consumption

It allows multiple instructions to be executed per clock cycle.

It increases memory bandwidth

It eliminates the need for virtual memory

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which memory management technique allows the execution of processes that are not entirely in memory?

Caching

Fragmentation

Direct Memory Access (DMA)

Paging.

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which interconnect topology is commonly used in modern multi-core processors?

Star topology

Bus topology

Torus topology

Ring topology.

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the main purpose of Direct Memory Access (DMA) in a computer system?

To allow the CPU to directly access cache memory

To enable peripherals to transfer data to memory without CPU intervention.

To improve the execution speed of programs

To manage power consumption in processors

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which of the following is a key characteristic of a NUMA (Non-Uniform Memory Access) system?

All processors share a single memory pool with equal access times

Each processor has its own local memory with varying access times to remote memory.

It is primarily used in mobile computing for energy efficiency

It eliminates the need for multi-threading

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the role of a Translation Lookaside Buffer (TLB) in memory management?

It provides an alternative to page tables

It stores frequently used instructions for faster execution

It speeds up virtual-to-physical address translation.

It prevents memory fragmentation

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