L5 Instruction Set Design and Computer Architecture

What is the primary purpose of Instruction Set Design (ISA)?

• To define the physical size of a processor

• To optimize the hardware layout of a computer

• To serve as an interface between hardware and software

• To improve the cooling system of a processor

Which of the following is NOT a design issue in Instruction Set Design?

• Operation repertoire

• Data types

• Instruction length

• Power supply efficiency

What distinguishes a Reduced Instruction Set Computer (RISC) from a Complex Instruction Set Computer (CISC)?

• RISC uses microprogramming, while CISC uses hard-wired control

• CISC executes one instruction per clock cycle, while RISC executes multiple

• RISC has a fixed instruction format, while CISC has variable lengths

• CISC uses compact instruction sets, while RISC uses complex instruction sets

What type of instruction set uses microprogramming for executing instructions?

• Reduced Instruction Set Computer (RISC)

• Complex Instruction Set Computer (CISC)

• Hybrid Instruction Set

• None of the above

Which of the following is an example of control flow activities in an instruction set?

• Adding two values in registers

• Copying data from memory to a register

• Jumping to a specific memory location

• Multiplying two data values

What is the primary function of a pipeline in computer architecture?

• To create multiple threads for execution

• To enhance processor performance by executing multiple instructions simultaneously

• To disable hyperthreading technology

• To increase CPU clock speed

What is the role of hyperthreading technology in a processor?

• To reduce the number of physical cores in the processor

• To allow multiple threads to be processed simultaneously by virtual cores

• To improve memory latency

• To disable the fetch unit in pipelining

How can hyperthreading technology be activated on a processor?

• By increasing the number of physical cores

• By enabling it through the BIOS settings

• By using the pipeline length of the CPU

• By modifying the device manager

Which of the following is NOT a stage in pipelining?

• Fetch

• Decode

• Write

• Kernel

What is a major complication in deep pipelining with many stages?

• It reduces processor latency

• Conditional branch instructions may require pipeline flushing

• The fetch unit becomes idle during instruction execution

• It eliminates the need for instruction scheduling