Fundamentals of Verilog

What is the basic structure of a Verilog module?

• module (input , output ); // assign statements // endmodule

• module (output , input ); // endmodule

• module (input , output ); // internal declarations // assign statements // always blocks endmodule

• module (input ); // internal declarations // always blocks // endmodule

What data types are commonly used in Verilog?

• boolean

• char

• wire, reg, integer, real, time, string, array

• float

Explain the difference between nets and regs in Verilog.

• Nets are for temporary values, and regs are for permanent values.

• Regs can have multiple drivers, whereas nets can only have one driver.

• Nets are used for storage, while regs are for connections.

• Nets are for connections (multiple drivers), and regs are for storage (single driver).

How do you declare a wire in Verilog?

• wire: myWire;

• reg myWire;

• int myWire;

• wire myWire;

What is the syntax for a basic AND gate in Verilog?

• assign output = input1 & input2;

• assign output = input1 + input2;

• output = input1 | input2;

• output <= input1 & input2;

How do you write a comment in Verilog?

• Use '#' for comments

• Use '/*' for single-line comments

• Use '//' for single-line comments and '/* ... */' for multi-line comments.

• Use '//' for multi-line comments

What is the purpose of the 'always' block in Verilog?

• The 'always' block is used for defining module parameters.

• The 'always' block is only for combinational logic.

• The 'always' block is used to declare variables in Verilog.

• The 'always' block is used to describe behavior that executes in response to signal changes.

Describe how to instantiate a module in Verilog.

• instance_name module_name (port1, port2);

• module_name instance_name port1, port2;

• module_name (instance_name, port1, port2);

• module_name instance_name (port1, port2, ...);

What is the function of an OR gate in digital logic?

• The function of an OR gate is to output true if at least one input is true.

• The function of an OR gate is to output true only when no inputs are true.

• The function of an OR gate is to output true only if all inputs are true.

• The function of an OR gate is to output false if at least one input is true.

How can you represent a NOT gate in Verilog?

• output = !input;

• assign output = input;

• output = input ? 0 : 1;

• assign output = ~input;