Computer Architecture Midterm Exam

Computer Architecture Midterm Exam

University

49 Qs

quiz-placeholder

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Computer Architecture Midterm Exam

Computer Architecture Midterm Exam

Assessment

Quiz

Computers

University

Hard

Created by

дестинезиа дестинезиа

FREE Resource

49 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In a typical memory hierarchy or bus system, can read and write operations be executed at the same time?

Yes, always-read and write are independent and parallel by design

No, never-memory can only handle one operation at a time

It depends on the hardware architecture and memory/bus design

Yes, but only if they target different addresses in cache

Only if the CPU supports dual-ported memory modules

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is DDR RAM (Double Data Rate Random Access Memory)?

A type of ROM used for permanent storage in embedded devices

A memory type that transfers data on both rising and falling edges of the clock signal

A cache memory integrated directly into the CPU for faster access

A legacy memory format used only in floppy disk controllers

A virtual memory technique used to expand RAM size on hard disks

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

RAM (Random Access Memory) is a volatile type of memory, meaning it loses its data when the power is turned off.

True

False

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the primary purpose of a Karnaugh Map (K-map) in digital logic design?

To represent the sequence of instructions in a processor pipeline

To visually simplify Boolean algebra expressions by grouping adjacent 1s

To convert binary numbers into hexadecimal format

To simulate real-time memory access in embedded systems

To generate truth tables for complex arithmetic operations

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which of the following best describes associative cache mapping?

Each block of main memory maps to exactly one location in the cache

Any block of main memory can be stored in any cache line

Cache blocks are grouped into sets, and each block maps to one set only

It uses the highest memory address bits as a direct index into the cache

It maps cache lines using page tables and virtual addresses

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the defining characteristic of associative cache mapping?

Each memory block is mapped to a specific, fixed location in the cache

The cache is divided into sets, and each block can only go into one assigned set

A memory block can be placed in any cache line, offering complete flexibility

Memory blocks are stored based on virtual addresses and page numbers

It uses a hashing function to calculate cache indices from memory addresses

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What best defines direct-mapped cache?

Every memory block can go into any cache line, offering maximum flexibility

Each memory block is mapped to a single, predetermined cache line based on address bits

Cache lines are grouped into sets, and memory blocks map to one of several cache lines in a set

Memory blocks are stored using virtual addressing for faster lookup

Cache data is organized dynamically using LRU-based hashing

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