CMOS Inverter Quiz

In a CMOS inverter, the pull-up network is composed of:

• NMOS transistor

• PMOS transistor

• Resistor

• Depletion-mode NMOS

What happens when the input to a CMOS inverter is at logic high (V_DD)?

• Both PMOS and NMOS are ON

• Both PMOS and NMOS are OFF

• NMOS is ON, PMOS is OFF

• PMOS is ON, NMOS is OFF

Which of the following is a major advantage of CMOS inverters over pseudo-NMOS inverters?

• Faster switching

• Higher static power consumption

• Zero static power consumption

• Higher gain

At the inverter threshold voltage (V_th), the CMOS inverter has:

• Maximum gain

• Minimum gain

• Both transistors OFF

• Output = Input

The output of a CMOS inverter is ideally:

• Floating

• Equal to input

• Complement of input

• Same as supply voltage

Which condition causes both PMOS and NMOS transistors in a CMOS inverter to conduct simultaneously?

• Input = 0 V

• Input = V_DD

• Input = V_DD/2

• Output = V_DD

Which of the following best describes the static power dissipation in a CMOS inverter?

• Occurs during logic high

• Occurs only during logic low

• Zero when input is static

• High for all inputs

The noise margin of a CMOS inverter is best when:

• Both transistors are OFF

• Input is far from threshold voltage

• Output swing is small

• Rise and fall times are unequal

Which factor improves the switching speed of a CMOS inverter?

• Reducing supply voltage

• Increasing load capacitance

• Increasing transistor sizes

• Using a resistive pull-up

Which region of operation applies to both PMOS and NMOS during switching at V_th?

• Cutoff

• Saturation

• Linear

• Weak inversion