Flip-Flop and Timing Parameters Quiz

What is the key difference between a D flip-flop and a JK flip-flop?

• D flip-flop has one input, while JK flip-flop has two inputs (J and K)

• D flip-flop cannot toggle, but JK flip-flop can

• Both (a) and (b)

• D flip-flop is faster than JK flip-flop

In a JK flip-flop, what happens when J=1 and K=1 with a clock pulse?

• Output Q becomes 1

• Output Q becomes 0

• Output Q toggles (changes state)

• Outputs Q and Q' become invalid

Setup time for a flip-flop is defined as:

• Time after clock edge for input to stabilize

• Time before clock edge for input to stabilize

• Time taken for output to change after clock edge

• Minimum clock pulse width required

Which flip-flop timing parameter prevents metastability?

• Propagation delay only

• Setup time only

• Both setup and hold time

• Clock-to-Q delay

A divide-by-4 frequency circuit requires how many flip-flops?

• 1

• 2

• 3

• 4

In D Flip-Flops, what happens when D=1 at positive edge-triggered?

• Output Q=1

• Output Q=0

• Output Q=0 and SET

• Output Q'=1 and RESET

Propagation delay, tPLH, measured from triggering edge of clock pulse to LOW-to-HIGH transition output

• True

• False

Hold time is the minimum time for the data to remain before the clock

• True

• False

Propagation delay in flip-flops is measured from:

• Input change to output change

• between the 50% clock level to the 50% output transition level

• Power-up to valid output

• Reset to normal operation

Which application exploits the toggle feature of JK flip-flops?

• Data storage registers

• Frequency division circuits

• Analog-to-digital converters

• Voltage regulators