Computer Architecture Quiz

The average time required to search a storage location in memory and obtain its contents is called:

• Access time

• Latency time

• Response time

• Reading time

Answer explanation

Access time refers to the average time required to search a memory storage location and retrieve its contents. It is a key performance metric in computer systems that measures how quickly the memory can be accessed by the processor.

• Latency time typically refers to the delay between initiating a request and starting to receive data but is not the same as access time.

• Response time includes both the access time and any other delays such as processing time or communication delays.

• Reading time might refer to the time taken specifically for the reading process but is not commonly used as a term for general memory access.

Which of the following statements with respect to K-segment pipelining are true?

• Maximum speedup that a pipeline can provide is k theoretically.

• It is impossible to achieve maximum speedup k in the k-segment pipeline.

• All segments in the pipeline take the same time in computation.

Answer explanation

The maximum speedup in a pipeline with k stages is theoretically k because each stage can ideally process one item per cycle, allowing for k items to be processed simultaneously. However, in practice, achieving this maximum speedup is difficult because of issues such as pipeline stalls (when one stage must wait for another to complete its operation) and unequal processing times across the stages.

This means that even though the theoretical speedup is k, the actual speedup is typically less than k.

The statement that all segments take the same time is also unrealistic because different operations in a pipeline often have different execution times.

Which of the following is/are true for Dynamic RAM (DRAM)?

• It is slower than static RAM (SRAM)

• Packing density is higher than Static RAM (SRAM)

• It's faster than Static RAM (SRAM)

• It requires data refreshing

Answer explanation

1. Dynamic RAM (DRAM) is slower than Static RAM (SRAM):
   DRAM requires periodic refreshing of data, which increases access times, making it slower than SRAM.

3. Packing Density of DRAM is higher than SRAM:
   DRAM uses a simpler memory cell structure (one transistor and one capacitor per bit), resulting in higher packing density compared to SRAM, which uses multiple transistors per cell.

5. DRAM is not faster than SRAM:
   SRAM operates faster because it does not need refreshing and has lower latency.

7. DRAM requires data refreshing:
   DRAM stores data in capacitors that gradually lose charge, requiring periodic refresh cycles to prevent data loss.

The microoperation which divides a signed binary number by 2 is:

• Circular shift

• Logical shift

• Arithmetic shift right

• Arithmetic shift left

Answer explanation

•Arithmetic shift right (ASR): This operation divides a signed binary number by 2, while maintaining the sign bit (i.e., preserving the negative or positive sign of the number). In a signed number, shifting the bits to the right effectively divides the number by 2, with the leftmost bit (sign bit) being replicated to maintain the sign.

•Circular shift: This operation moves bits around in a circle (or ring), so no division or multiplication by 2 happens.

•Logical shift: A logical shift moves bits left or right and fills the vacant positions with zeros, but it does not preserve the sign of the number.

•Arithmetic shift left: This operation multiplies a signed number by 2, not divides.

The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of:

• Flags and Counters

• Registers and Counters

• Flags and Registers

• Flags, Registers, and Counters

Answer explanation

To effectively diagnose faults in the micro-program control unit, it is crucial to maintain and monitor the contents of flags, registers, and counters. These components hold the essential information regarding the state of the system, which can help in identifying issues such as incorrect execution, improper data handling, or control flow problems.

• Flags provide status information about the processor, such as zero, carry, sign, or overflow conditions.

• Registers store data and intermediate results, enabling the control unit to process instructions correctly.

• Counters track the sequence of operations, especially the instruction counter, which helps in understanding the program flow and detecting errors.

The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as:

• DMA (Direct Memory Access)

• IOP (Input-Output Processor)

• Serial Interface

• Parallel Interface

Answer explanation

(A) DMA (Direct Memory Access):
This is correct. DMA is a mechanism that allows peripherals to communicate with memory directly, without involving the CPU. It enables fast data transfer by bypassing the CPU, which increases overall system performance.

(B) IOP (Input-Output Processor):
This is correct. An IOP is responsible for managing the input/output operations and can also handle direct memory access between peripherals and memory. It controls the data transfer and allows efficient interaction between the peripheral and memory without requiring constant CPU involvement.

Arrange the following in the increasing order of complexity:

A. I/O Module
B. I/O Processor
C. I/O Channel
D. DMA

• A, B, C, D

• A, D, C, B

• C, D, A, B

• D, C, B, A

Answer explanation

The increasing order of complexity for I/O systems generally follows this reasoning:

1. I/O Module (A):

   • Least complex. An I/O module is a simple component that handles the transfer of data between the processor and external devices. It typically performs basic functions like data transfer and basic control functions, but it does not have advanced capabilities like processing or managing complex operations.

2. DMA (D) - Direct Memory Access:

   • Moderate complexity. DMA allows devices to communicate with memory directly, bypassing the CPU, to increase efficiency. While more complex than an I/O module, it's still primarily focused on data transfer, without the full control and management that a dedicated processor or channel would provide.

3. I/O Channel (C):

   • More complex. An I/O channel is a hardware interface between the I/O module and the processor. It has more advanced capabilities, such as supporting multiple devices and being able to manage the control of multiple data transfers. It is typically used in larger systems that need more extensive data movement.

4. I/O Processor (B):

Most complex. An I/O processor is essentially a processor that manages I/O operations. It has its own memory and can execute instructions independently to handle complex I/O operations. It offloads work from the main CPU by managing I/O operations, making it the most complex of the listed components.

Match list I and List II

List I

A) Handshaking

B) Programmed I/O

C) Interrupt driven I/O

D) I/O Processor

List II

(i) I/O interface informs the CPU that the device is ready for transfer

(ii) Requires two control signals working in opposite directions

(iii) Has local memory & control large set of I/O devices

(iv) Requires CPU to check the I/O flag & perform transfer

• A-I, B-II, C-III, D-IV

• A-II, B-IV, C-III, D-I

• A-II, B-IV, C-I, D-III

• A-IV, B-III, C-II, D-I

Answer explanation

Handshaking (A) involves two control signals working in opposite directions (II). Programmed I/O (B) requires the CPU to check the I/O flag and perform the transfer (IV). Interrupt driven I/O (C) informs the CPU that the device is ready for transfer (I). I/O Processor (D) has local memory and control for managing a large set of I/O devices (III).

Which of the following is correct statement?

• In memory-mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words.

• The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.

• In asynchronous serial transfer of data the two units share a common clock.

• In synchronous serial transmission of data the two units have different clocks.

Answer explanation

in memory-mapped I/O, the CPU can manipulate I/O data residing in the interface registers, but these registers are typically part of the memory space, not separate from it. Memory-mapped I/O uses the same address space as regular memory. isolated I/O uses distinct address spaces for memory and I/O operations.

This means the I/O addresses do not affect the address range for memory operations, ensuring that the two do not overlap.

in asynchronous serial transfer, the two units do not share a common clock. Instead, data is transmitted with start and stop bits to synchronize the data transfer. synchronous serial transmission requires both units to share a common clock to ensure data is transmitted at the correct timing intervals.

Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory-mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory-mapped I/O

• I/O protection is ensured by operating system routines.

• I/O protection is ensured by a hardware trap.

• I/O protection is ensured during system configuration.
  
  

• I/O protection is not possible.

Answer explanation

In memory-mapped I/O, I/O devices are treated as if they are memory locations. Since there are no special I/O instructions, the operating system must manage access to these memory-mapped I/O locations to prevent unauthorized access.

This is achieved by implementing proper protections in the operating system routines, ensuring that user programs cannot directly access or manipulate I/O devices. Therefore, I/O protection is enforced by the operating system, making option "I" the correct answer.