
Computer Architecture 14-18 Quiz
Authored by Chị Đực
English
University
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40 questions
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1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
With ________ instructions are simultaneously issued from multiple threads to the execution units of a superscalar processor.
chip multiprocessing
SMT
coarse-grained multithreading
single-threaded scalar
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
_________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on.
Rollover
Chaining
Pipelining
Passive standby
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.
output dependency
procedural dependency
true data dependency
antidependency
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
With _______, register banks are replicated so that multiple threads can share the use of pipeline resources.
scalar
pipelining
SMT
superscalar
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
A ________ instruction can be used to account for data and branch delays.
NOOP
all of the above
JUMP
SUB
6.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses.
resource conflict
antidependency
out-of-order completion
in-order issue
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
All MIPS R series processor instructions are encoded in a single ________ word format.
4-bit
16-bit
8-bit
32-bit
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