50 MCQs - Verilog Modeling

Which of the following best describes structural modeling in Verilog?

• Uses continuous assignments to describe behavior

• Describes circuits using interconnected gates and modules

• Uses initial blocks for simulation

• Describes timing delays only

Which model in Verilog represents circuits as a network of interconnected gates?

• Dataflow

• Structural

• Behavioral

• Testbench

In structural modeling, modules are connected using:

• Wires

• Reg

• Always blocks

• Parameters

The truth table of a combinational logic circuit defines:

• Timing delays

• Output for all input combinations

• Gate strengths

• Sequential behavior

Which of the following is NOT used in structural modeling?

• Modules

• Gate primitives

• Always blocks

• Interconnections

Which of the following is a gate-level primitive in Verilog?

• assign

• and

• initial

• always

Gate-level modeling is mainly used for:

• High-level algorithm design

• Describing circuit behavior only

• Connecting predefined gates

• Describing FSMs

Which Verilog keyword is used to instantiate a gate?

• gate

• primitive

• module

• and/or/not

Tri-state buffers in Verilog are represented using which primitive?

• bufif1, bufif0

• and, or

• xor, xnor

• nand, nor

Which net type is commonly used for connecting gate instances?

• reg

• wire

• parameter

• integer