Analytical MCQs: Computer Architecture

A processor has a 5-stage pipeline. If each stage takes 1 ns, what is the ideal throughput?

• 1 instruction per 5 ns

• 5 instructions per ns

• 1 instruction per ns

• 5 instructions per 5 ns

In a system with multiple buses, which configuration minimizes contention during simultaneous memory and I/O operations?

• Single shared bus

• Separate memory and I/O buses

• Daisy-chained bus

• Ring topology

A pipeline has a branch instruction every 5 instructions and a misprediction penalty of 3 cycles. What is the average CPI if ideal CPI is 1?

• 1.0

• 1.

• 2.0

• 3.0

A superscalar processor can issue 4 instructions per cycle but only 2 are executed due to dependencies. What is the issue efficiency?

• 25%

• 50%

• 75%

• 100%

Which hazard type is most likely to occur in a loop with dependent arithmetic operations?

• Structural hazard

• Data hazard

• Control hazard

• Cache hazard

A processor uses out-of-order execution and encounters a RAW hazard. What mechanism resolves this?

• Branch prediction

• Register renaming

• Instruction flushing

• Cache invalidation

In speculative execution, what happens if the prediction is incorrect?

• The pipeline continues

• The instruction is skipped

• The pipeline is flushed and correct path is executed

• The CPU halts

Which of the following best explains why SMT improves throughput in a stalled pipeline?

• It increases clock speed

• It adds more ALUs

• It allows another thread to use idle resources

• It reduces instruction size

A system with hyper-threading shows increased performance in multi-threaded workloads but not in single-threaded ones. Why?

• Hyper-threading increases single-thread latency

• It only activates on dual-core systems

• It shares execution units across threads

• It disables cache for single threads

Which pipeline hazard can be mitigated using forwarding (bypassing)?

• Control hazard

• Structural hazard

• Data hazard

• Instruction hazard