FT1-21ECC303T

What will be printed by the following code? module test; reg [3:0] a = 4'b1101; initial $display("%b", a >> 1); endmodule

• 1101
• 110
• 1011
• 11

In Verilog, what is the output of this code? assign y = ~(4'b1010 & 4'b1100);

• 4'b0101
• 4'b0011
• 4'b1111
• 4'b0110

Consider: always @(*) begin a = 1; b = a + 2; end — What is the value of `b` after execution?

• 1
• 2
• 3
• 4

Which of the following code correctly describes a 2-to-1 MUX in behavioral modeling?

• assign y = s ? d1 : d0;
• always @(s or d1 or d0) y = s ? d1 : d0;
• always @(posedge clk) y <= d1;
• y = s ? d1 : d0;

What is the output of: `assign y = ^4'b1101;

• 1
• 0
• x
• z

In the code: reg [3:0] a = 4'b1001; initial a = a << 1; what is `a` after execution?

• 1001
• 10
• 1010
• 100

For `assign y = {2{2'b10}}; , what is `y`?

• 1010
• 101010
• 10101010
• 10

What does the following code implement? `assign y = ~(a ^ b);`

• XOR
• XNOR
• AND
• OR

What is the output for: `assign y = (3'b101 == 3'b101);`

• 0
• 1
• x
• z

Given: always @(posedge clk) q <= d; — What is implemented?

• Combinational logic
• D Flip-Flop
• Latch
• Counter