module 2

Which of the following techniques is used to reduce cache miss penalty?
A. Increasing associativity
B. Critical word first and early restart
C. Increasing cache block size indefinitely
D. Write-through policy only

• Increasing associativity

• Critical word first and early restart

• Increasing cache block size indefinitely

• Write-through policy only

A victim cache is mainly used to:

• Store dirty blocks before write-back

• Reduce conflict misses

• Increase block size without increasing latency

• Store data for prefetching

Which of the following is true about DRAM compared to SRAM?

• DRAM is faster but more expensive

• DRAM is slower but denser and cheaper

• DRAM uses flip-flops to store bits

• DRAM requires no refresh cycles

In virtual memory, the translation from virtual address to physical address is handled by:

• Cache controller

• Page table and TLB

• DMA controller

• Instruction decoder

One key advantage of using virtual machines is:

• Lower instruction execution latency

• Better direct hardware control by the user process

• Isolation between multiple OS instances

• Elimination of context switching

Which of the following is NOT a challenge in designing efficient virtual machines?

• Privileged instruction handling

• Memory virtualization overhead

• Instruction fetch decoding

• Transparent resource sharing

The Intel Core i7 uses which cache inclusion policy?

• Exclusive L2 cache

• Inclusive L3 cache

• Non-inclusive, non-exclusive L3 cache

• Victim cache for L2

The ARM Cortex-A8 typically uses:

• Separate L1 instruction and data caches

• Unified L1 cache

• No L2 cache

• Fully associative L1 cache

Which is true regarding memory hierarchy in Intel Core i7 vs ARM Cortex-A8?

• Intel Core i7 uses an out-of-order superscalar design, while Cortex-A8 is in-order

• Both have unified L1 caches

• ARM Cortex-A8 has a shared L3 cache

• Intel Core i7 does not use TLBs

Increasing cache block size generally reduces:

• Compulsory misses

• Conflict misses

• Capacity misses

• Write-back frequency